library ieee;

use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;


-- Test bench for the Fifo buffer
	
entity test_bench is
end entity test_bench;

architecture test_fifo of test_bench is
	signal write_en, read_en, clk, reset, full, empty : std_logic;
	signal data_in : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
	signal data_out : std_logic_vector(31 downto 0);
	
begin
	dut: entity work.fifo_buffer(behav)
		port map(data_in, write_en, read_en, clk, reset, full, empty, data_out);
		
	
	--write process test bench
	write : process is 
	begin
		write_en <= '1'; wait for 20ns;
		data_in <= data_in + 1;   
		write_en <= '0'; wait for 20ns;	
	end process write;	
	
	--read process test bench
	read : process is 
	begin	
		read_en <= '0'; wait for 20ns;	 	 
		read_en <= '1'; wait for 20ns;
	end process read;	
	
	--clock process test bench
	clock : process is
	begin
		clk <= '0'; wait for 5ns;
		clk <= '1'; wait for 5ns;
	end process clock;	 
	
	--clock process test bench
	reset_proc : process is
	begin
		reset <= '0'; wait for 200ns;
		--reset <= '1'; wait for 10ns;
		--reset <= '0'; wait for 200ns;
	end process reset_proc;
end architecture test_fifo;